Reprogrammable FPGAs have been available commercially for several years. The best known commercial family of FPGAs are those from Xilinx, Inc. One class of these devices uses Static Random Access Memory (SRAM) cells to hold control bits which control their configurations. Each SRAM cell controls one or more transistors at the configurable points in an FPGA or serves as one or more entries in a lookup table. (The configuration memory cells collectively determine what functions the FPGA will implement.)
The present invention will be described in connection with SRAM FPGAs. The configuration of the FPGA is typically loaded from a non-volatile configuration memory into the SRAM configuration memory cells when power is applied to the system.
Some commercially available SRAM FPGAs use data and address lines to access the configuration memory in a way similar to that used to access any random access memory. With an addressable configuration memory, an external processor can perform word-wide read or write operations on the registers of the user's design without having to re-load other parts of the configuration data. In such systems, a small portion of the configuration memory can be changed rapidly, and the remaining configuration memory may remain undisturbed. Thus the configuration memory interface allows high bandwidth (high speed) communication between the processor and the FPGA.
In present RAM addressable FPGAs some of the pins of the FPGA are dedicated to address lines, data lines, and other control lines for loading the configuration memory, while other pins are dedicated to input and output of user logic. FIG. 1 shows such an FPGA chip and the relationships between external pads, the FPGA user logic structures, and the configuration memory which configures the user logic. It is convenient to visualize the FPGA as formed in first and second stories, a first story holding the configuration information which selects the functions performed by the FPGA, and a second story which performs the function selected by the user. FIG. 1 illustrates the FPGA in this manner. (Physically, the configuration memory and the user logic are formed on the same substrate of an integrated circuit structure. This structure is described in PCT application serial No. WO 94/10754 published May 11, 1994.)
As shown in FIG. 1, some of the pads are for accessing user logic 19 and others are for addressing and loading configuration memory 25. The pad drivers 18 are configured by a user-generated enable signal to determine whether a particular user logic pad 16 is an input pad, an output pad, or unused. Switches such as switch 15 are configured by the underlying configuration memory 25 to transfer signals between the pad drivers 18 and the internal user logic 19. Such internal user logic is discussed in detail by the present inventor in Patent Cooperation Treaty patent application serial No. WO 94/10754 published 11 May 1994. Pads R0 through R3, R/W, CE, CK, RST, C0 through C2, D0 through D7 and their related pins (not shown in FIG. 1) are dedicated to the configuration function. A commercially available device typically has more pads for both configuration and user logic than shown in FIG. 1.
Configuration memory 25 is loaded by addressing a memory cell or memory word as is done in a conventional RAM. Row and column address busses 22 and 27 carry address signals which are decoded by row and column decoders 21 and 26, and connect a selected word of configuration memory 25 to configuration data bus 23 to be read or written. Pads D0 through D7 are coupled to configuration data bus 23.
FIG. 2 shows the relationship between the address and data busses, the row and column decode structures, the eight bit drivers associated with each word, and the data locations in the configuration memory array 25. Such structures are well known in the art. Betty Prince in "Semiconductor Memories".COPYRGT. 1983, 1991 by John Wiley & Sons discusses such structures at pages 149-174.
Also shown in FIG. 1 is memory load control unit 24. Control unit 24 enables row and column decoders 21 and 26 in response to well known clock, chip enable, and reset signals from pads CE, CK, and RST respectively. Memory control unit 24, in response to a read/write signal on pad R/W, determines whether pads D0 through D7 will have an input configuration for writing or an output configuration for reading data bus 23.
If the structure of FIG. 1 is to be reconfigured or partially reconfigured during operation, an external device such as a microprocessor addresses portions of the configuration memory and loads new data into those locations.
In some FPGAs, the logic available to a user in the FPGA includes both combinational logic which may implement a user-selected function, and registers which the user may store values. Thus the FPGA includes many configuration memory cells (which may be flip flops or latches) and some user logic registers (which are usually flip flops).
The user may wish to read and write the user logic registers directly, for example from a microprocessor, especially when debugging a design. Or the user may wish to reserve certain registers for loading data from an external position and not allow these registers to be written from internally generated values.